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Itanium gets an update ahead of dual-core debut

Itanium gets an update ahead of dual-core debut

Intel plans to improve the speed of the front-side bus on its high-end Itanium 2 processor next week, in preparation for the launch of its first dual-core Itanium processors, according to sources familiar with the company's plans.

The company will announce two new Itanium 2 processors on Monday with Hitachi Ltd., which demonstrated a chipset that supported a 667MHz front-side bus at the Spring Intel Developer Forum in March. One processor will be available with 9M bytes of Level 3 cache memory, while the other will come with 6M bytes of cache memory. Both chips will run at 1.66GHz, sources said.

An Intel spokeswoman declined to comment on unannounced products.

Itanium is a 64-bit processor based on an entirely different instruction set than the x86 instruction set used by the vast majority of the world's PCs and servers. Intel had originally hoped Itanium and its EPIC (explicitly parallel instruction computing) instruction set would help it usher in the 64-bit era in server computing, but tepid customer reaction in the first five years of its existence has led Intel to target the chip as a high-end replacement for older servers using RISC (reduced instruction set computing) processors

Intel has addressed the broader volume server market by following rival Advanced Micro Devices Inc.'s lead in releasing a chip that uses 64-bit extensions to the x86 instruction set, and providing users with a simpler path to 64-bit computing than converting their applications to Itanium.

Improving Itanium's front-side bus speed will help the chip's performance on applications that require large amounts of data shuffled from the main memory to the CPU (central processing unit), said Kevin Krewell, editor in chief of The Microprocessor Report in San Jose, California. The enhancement will have implications on Intel's upcoming dual-core Itanium processor, code-named Montecito, which is expected in the fourth quarter, he said.

Montecito consists of two Itanium processor cores that will share a single front-side bus in some server designs, or take advantage of dual-independent buses in others. With all those extra processing resources competing for the same pathway to the memory, Intel needed to improve the speed of this link in order to take full advantage of both cores, Krewell said.

Itanium is primarily used in multiprocessor servers for high-performance computing or enterprise data centers. Hewlett-Packard is Intel's largest partner for Itanium, but Hitachi, Fujitsu, and IBM also dabble in the Itanium server market.

Hitachi will use the new chips in forthcoming versions of its BladeSymphony blade servers, sources said.


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