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MIT uses nanotech to shrink chips to 25nm

MIT uses nanotech to shrink chips to 25nm

Researchers find a way to build cheaper, more powerful processors

MIT researchers have discovered how to use nanotechnology to significantly shrink computer chips, making them cheaper and more powerful.

The new technique will enable manufacturers to produce 25-nanometer (nm) chips, which is a huge leap considering that late last year Intel made its first move from a 65nm process to 45nm. Intel has already said it hopes to move to 32nm-processors sometime in 2009; A 25nm-chip would be one level below that.

"The goal is to make smaller patterns on the chips," said Ralf Heilmann, a research scientist at MIT. "The integrated circuits and transistors that are the core of the chips - the smaller you can make them the faster they are and the more you can pack on a single chip. They're cheaper and more powerful at the same time."

Heilmann said MIT has patented the technique, and that different semiconductor companies, whom he would not name, have shown interest in it.

The new technique involves nanoscale lithographic technology that makes finer patterns of lines, used to make up the circuits, on the chips. Optical lithography uses light to transfer the pattern onto the chip. In the past, Heilmann said, chip makers tried using shorter wavelengths of light to make the lines closer to together. That, technique, has its limits.

Heilmann said the MIT researchers used longer wavelengths to make 200nm lines with 200nm of space in between them. They would then take the same line template and simply move it over, laying down new lines and cut the space in between them in half. They do this over and over until they get the lines and spaces down to 25nm.

That gives them four times the pattern density and enables them to pack in four times as many features, like wires, conductors and transistors.

"If you can speed the chip up while shrinking it at the same time, you get a big performance bump," said Dan Olds, principal analyst with the Gabriel Consulting Group. "This looks like it makes shrinking below 32nm work reasonably well from a cost and yield perspective...and that's a very interesting prospect that has broad implications. The key point is that their process works at the cutting edge -- less than 45nm -- of performance, rather than just being a cheaper way to produce old chips."

Heilmann said he believes the process could be adjusted to produce chips smaller than 25nm. "It's certainly a possibility," he said.

The MIT project team worked in the Space Nanotechnology Laboratory of the MIT Kavli Institute of Astrophysics and Space Research. They received financial support from NASA and the National Science Foundation.


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